Portable electronic memorandum device

ABSTRACT

A portable electronic memorandum device has a memory for storing character data items. When a switch is operated, all the address areas of the memory are designated so as to sequentially read out all the character data items stored therein. All the character data items are then sequentially displayed on a display. After all the character data items stored in all the address areas are sequentially displayed on the display, the address of the memory is updated by the operation of switches, thus performing an edit operation of the character data items.

BACKGROUND OF THE INVENTION

This invention relates to a portable electronic memorandum devicecomprising a data memory which can electronically read/write characterdata items such as telephone numbers, addresses, schedules and the like.

Modern electronic watches and small electronic calculators can storecharacter data items such as names, telephone numbers, addresses,schedules, and the like by means of a data input means from a keyboardin addition to its original function. A desired character data item canbe read out for display.

For example, a device disclosed in U.S. Pat. No. 3,999,050 has akeyboard consisting of letter, numerial, and function keys and stores aname, a telephone number and a time to call in a data memory by means ofthe above keys. When it is the time to make a predetermined call, thename and telephone number to call are displayed on a display unit.

Another prior art device disclosed in U.S. Pat. No. 4,117,542 comprisesa keyboard consisting of keys for designating letters, numerals andfunctions, and stores telephone numbers, street addresses, appointments,an agenda and the like in a data memory means. When letters representinga desired name are keyed in, the telephone number and the address of thecorresponding person are read out from the data memory means so as todisplay them on a display unit.

In these prior art devices, the data is written/read from the datamemory by operation of the keys on the keyboard, resulting in a complexinput/output circuit configuration. Therefore, it is difficult to applythese techniques to small electronic equipment, such as wristwatches.

SUMMARY OF THE INVENTION

The present invention has been made in consideration of the abovedrawbacks of the prior art, and has as its object to provide a portableelectronic memo random device which can simplify input/output operationsof telephone numbers, names, messages and the like and an input/outputcircuit therefor, and which can be applied to small electronic equipmentsuch as a wristwatch.

In order to achieve the above object according to the present invention,there is provided a portable electronic memorandum device comprisinginput means for inputting a character data item including at leastcharacter data; character data item storing means, having a plurality ofaddress areas, for storing in the respective address areas the characterdata items inputted by the input means; switching means operative forreading the character data item stored in the character data itemstoring means so as to display it; character data item read out controlmeans for sequentially designating all the address areas of thecharacter data item storing means every time the switching means isoperated so that all the character data items stored in the respectiveaddress areas are sequentially read out; optical displaying means forsequentially displaying the character data items read out by the readout control means; and address designation changing means forsequentially designating the address areas in which the character dataitems are stored when the switching means is operated again after allthe address areas in which the character data items are stored aredesignated by said switching means and all the character data items havebeen displayed on the optical displaying means. With the abovearrangement, the portable electronic memorandum device according to thepresent invention can write/read a character data item such as a name bya sequential address designation to/from a character data item memorywith a simple key operation, and an input/output circuit can also besimplified. For this reason, the device can be applied to smallelectronic devices, such as a wristwatch. Furthermore, when thecharacter data item is read, only the character data item stored need beretrieved. Thus, when the retrieval operation of the character data itemto be read ends, even if the remaining memory areas are present, anextra sequential retrieval operation is not performed, and the addressdesignating operation can be switched to designate the first address atwhich the character data item is stored, thus simplifying the retrievaloperation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing an electronic wristwatch to which thepresent invention is applied;

FIG. 2 is a view showing an arrangement of a display unit 1 shown inFIG. 1;

FIG. 3 is a block circuit diagram of the electronic wristwatch shown inFIG. 1;

FIG. 4 is a block circuit diagram showing in detail a switching unit 22and a switching control 16 shown in FIG. 3;

FIG. 5 is a block circuit diagram showing in detail a data memory 15;

FIG. 6 shows a memory map of a RAM 41 shown in FIG. 5;

FIGS. 7A to 7C are representations for explaining changes in the displaystates of the display unit by the operation of a switch S1;

FIGS. 8A and 8B are representations showing display states of a hyphenon the display unit;

FIG. 9 is a view showing an arrangement according to another embodimentof the present invention for executing various functions by means of aROM storing a microprogram;

FIG. 10 is a view of an arrangement showing a RAM 111 in FIG. 9;

FIG. 11 is a general flow chart of the circuit shown in FIG. 9;

FIGS. 12A and 12B together show a flow chart of a write operation in thecircuit shown in FIG. 9;

FIG. 13 is a flow chart of a read operation in the circuit shown in FIG.9;

FIG. 14 is a representation showing changes in display states on thedisplay unit in accordance with a switching operation between timepieceand memory modes;

FIG. 15 is a representation showing changes in display states on thedisplay unit in the write mode and

FIG. 16 is a representation showing changes in display states on thedisplay unit in the read mode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the present invention will be described with referenceto the accompanying drawings. FIG. 1 is a plan view of an electronicwristwatch with a data memory function. Push-button switches S1 to S4are provided at two side portions of a watch casing. A liquid crystaldisplay unit 1 is provided on the upper surface of the watch casing, andpush-buttons switches S5 and S6 are provided below the display unit 1.

The display unit 1 has an arrangement shown in FIG. 2. The display unit1 comprises a matrix display portion 1A having 6 digits each consistingof (5×5) dots at an upper portion thereof, a sub digital display portion1B of 6-digit 8-segment displays at an intermediate portion thereof, amain digital display portion 1C of 6-digit 8-segment displays at a lowerportion thereof, and an alarm ON mark 1D.

A circuit configuration will be described hereinafter with reference toFIGS. 3 to 5. FIG. 3 is a block circuit diagram of the overallelectronic watch. A reference clock signal generated from an oscillator11 is supplied to a frequency divider/timing signal generator 12. Thegenerator 12 supplies a 1P/1s signal (timing clock) to a time counter13, and also supplies a display timing signal a to a display controller14. Furthermore, the generator 12 supplies a timing signal b to a datamemory circuit 15 and a switching controller 16. The time counter 13counts the 1P/1s signal so as to obtain time data of hour, minute,second and data of year, month and day. The time and date data obtainedis supplied to the display controller 14 through a gate circuit 17 so asto be converted into display data. Thereafter, the display data issupplied to the display unit 1 and displayed. The time data obtained bythe time counter 13 is also supplied to an alarm circuit 18. When thealarm circuit 18 detects the coincidence between preset alarm time dataand the time data supplied from the time counter 13, it supplies analarm signal to an alarm unit 19, thereby generating an alarm. The alarmtime data is supplied to the display controller 14 through a gatecircuit 20 so as to be converted into display data. The display data isthereafter supplied to the display unit 1 to be displayed thereon. Thedata memory circuit 15 can store name and telephone number data. Dataread out from the data memory circuit 15 is supplied to the displaycontroller 14 through a gate circuit 21 to be converted into displaydata, and thereafter is supplied to the display unit 1 to be displayedthereon. When the circuit 15 is selected, a signal 15a is generated fromthe circuit 15 as a display control signal and is supplied to thedisplay controller 14 as will be described later. The switchingcontroller 16 receives a switching signal generated from the switchingunit 22 having the above-mentioned switches S1 to S6. The controller 16supplies a time correction signal c, an alarm setting signal d, and adata set/read signal e to the counter 13, the alarm circuit 18 and thedata memory circuit 15, respectively. The controller 16 also supplies agate control signal f to the gate circuits 17, 20 and 21 so as toselectively enable them.

FIG. 4 shows a configuration of the switching unit 22 and the switchingcontroller 16 in detail. In the switching unit 22, the switch S1 is amode switch for selectively switching a timepiece mode for displaying acontent of the counter 13, a telephone number display mode fordisplaying a content of the data memory circuit 15, and an alarm timedisplay mode for displaying a content of the alarm circuit 18. Theswitch S2 is provided for setting or releasing a correction (set) modeof the data in the above three modes. The switch S3 is a digit selectionswitch for selecting digits to be corrected or set in the correction(set) mode. The switch S4 is an increment switch for incrementing acontent of the selected digit by one. Furthermore, the switches S5 andS6 are used for sequentially accessing name and telephone number datastored in the data memory circuit 15 in the telephone number displaymode. The switch S5 is a +1 switch for accessing forward, i.e.,accessing the next telephone number data. The switch S6 is a (-1) switchfor accessing backward, i.e., accessing the previous telephone numberdata. Thus, outputs from the switches S1 to S6 cause correspondingone-shot circuits 23 to 28 in the switching controller 16 to generatepulse signals. The pulse signal from the circuit 23 is supplied to amode selector 29. The selector 29 selects one of the timepiece mode, thetelephone number display mode and the alarm time display mode incorrespondence with bits 1 to 3 of the signal. Thus, the selector 29generates one of the signals 29a to 29c as th gate control signal f soas to enable one of the gate circuits 17,20 and 21. A bit 1 output fromthe selector 29 is supplied to AND gates 30 to 32, a bit 2 output issupplied to AND gates 36 to 40, and a bit 3 output is supplied to ANDgates 33 to 35, respectively. A pulse signal from the one-shot circuit24 is supplied to a T input terminal of a trigger flip-flop (T-FF) 9 andits output is inverted. A Q output of the T-FF 9 is supplied to the ANDgates 30, 33 and 36. Furthermore, an output pulse from the one-shotcircuit 25 is supplied to the AND gates 31, 34 and 37, an output pulsefrom the one-shot circuit 26 is supplied to the AND gates 32, 35 and 38,an output pulse from the one-shot circuit 27 is supplied to the AND gate39 and an output pulse from the one-shot circuit 28 is supplied to theAND gate 40. The outputs from the AND gates 30 to 32 are the timecorrection signals c described above. An output c1 from the AND gate 30is a signal for enabling the time correction state, an output c2 fromthe AND gate 31 is a digit selection signal and an output c3 from theAND gate 32 is a correction signal for incrementing a content of theselected digit. Similarly, the outputs from the AND gates 33 to 35 arethe alarm set signals d described above. An output d1 from the AND gate33 is a signal for enabling the alarm setting state, an output d2 fromthe AND gate 34 is a digit selection signal, and an output d3 from theAND gate 35 is a set signal for incrementing a content of the selecteddigit. The outputs from the AND gate 36 to 40 and the bit 2 output fromthe mode selector 29 are data set/read signals e. The bit 2 outpt e1from the mode selector 29 is a data read signal in the telephone numberdisplay mode, an output e2 from the AND gate 36 is a signal for enablingthe setting of the name and telephone number data, an output e3 from theAND gate 37 is a digit selection signal, an output 34 from the AND gate38 is a set signal for incrementing a content of the selected digit, anoutput e5 from the and gate 39 is a read signal for reading dataforward, an output e6 from the AND gate 40 is read signal from readingdata backward.

A configuration of the data memory circuit 15 will be described withreference to FIG. 5. A random-access memory (RAM) 41 constitutes thedata memory and has a structure shown in FIG. 6. Each digit addressregion of the RAM 41 comprises a character data storing portion whichcan store six letters and a numerical data storing portion which canstore 12 numerals. The name data is stored in the character data storingportion and the telephone number data is stored in the numerical datastoring portion. A row address of the RAM 41 is designated by count dataof an address counter 42, and data write/read operations are carried outwith respect to the designated address. The address counter 42 consistsof an up/down counter. When the signal e5 is supplied to the counter 42through an counter 42 through an OR gate 43, the count of the counter 42is incremented by one, and when the signal e6 is supplied thereto, thecount is decremented by one. The (name and telephone number) data readfrom the RAM 41 is transferred to a buffer 45 through an AND gate 44. Inthis case, the AND gate 44 is enabled when the signal e5 or e6 issupplied thereto through an OR gate 46. The AND gate 44 is also enabledwhen the signal e1 is supplied to a rising detector 47 and a one-shotpulse generated synchronously with the rising of the signal e1 issupplied thereto through the OR gate 46. The buffer 45 can store nameand telephone number data, and has a 6-digit character data storingportion 45a for storing the name data and a 12-digit numerical datastoring portion 45b for storing the telephone number data. Thus, thedata written in the buffer 45 is supplied to the display unit 1 throughthe gate circuit 21 to be displayed thereon.

The signal e2 enables AND gate 48 to 50 so as to allow the AND gates 48and 49 to generate the signal e4 and the AND gate 50 to generate thesignal e3, respectively. The output from the AND gate 48 is supplied toa character generator 51, and the output from the AND gate 49 issupplied to a numerical data generator 52. The generator 51 sequentiallygenerates one of the letters "A" to "Z" every time the signal e4 issupplied from the AND gate 48. The generator 52 sequentially generatesone of the numerals "0" to "9" every time the signal e4 is supplied fromthe AND gate 49. The output from the AND gate 50 is supplied to a digitselector 53. The selector 53 selects a digit of the buffer 45, andsequentially generates a digit selection signal every time the signal e3is supplied from the AND gate 50 so as to enable one of thecorresponding AND gates 54a1 to 54a6 and 54b1 to 54b12. The AND gates54a1 to 54a6 correspond to respective digits in the character datastoring portion 45a of the buffer 45 and transfer the character datagenerated from the character data generator 51 to the correspondingdigits of the buffer 45. The AND gates 54b 1 to 54b12 correspond torespective digits of the numerical data storing portion 45b of thebuffer 45 and transfer the numerical data generated from the numericaldata generator 52 to the corresponding digits of the buffer 45. Contentsof the buffer 45 are supplied not only to a data empty detector 55 andan error data detector 56 but also to a comparator 58 through an ANDgate 57. The detector 55 detects presence/absence of the datacorresponding to the respective digits of the buffer 45, and generates adetection signal corresponding to each digit of the buffer 45 as thedisplay control signal 15a mentioned above. When the display controlsignal 15a is supplied to the display controller 14, the controller 14causes sub and main digital display portions 1A and 1B of the displayunit 1 to display hyphens on the display digits corresponding to thedata empty digits in the numeral data storing portion 45b of the buffer45. When the detector 55 detects that none of the digits of the buffer45 has data, it generates a signal G. The signal G enables an AND gate59 which generates the signal e5 which is supplied to a clear terminalof the address counter 42 through an OR gate 60. The data error detector56 checks if the data written in the buffer 45 is data of apredetermined format. The detector 56 detects the date of thepredetermined format such as telephone number data which does not start"0" (in Japan, the telephone numbers start from "0"), name data whichconsist of six "A"s, and the like. When error data is detected, thedetector 56 generates a signal of high level (logic level "1") which issupplied to the AND gate 57 through an inverter 61.

The signal e2 is also supplied to a falling detector 62. The fallingdetector 62 generates a one-shot pulse in synchronism with the fallingof the signal e2. The output pulse from the detector 62 is supplied tothe clear terminal of the address counter 42 through the OR gate 60 andis also supplied to an S input terminal of a SR flip-flop (SR-FF) 63. AQ output from the SR-FF 63 enables an AND gate 64 which generates asignal of 16 Hz. The 16-Hz signal from the AND gate 64 is supplied tothe address counter 42 through the OR gate 43, thereby incrementing acontent thereof by one. The 16-Hz signal is supplied to the RAM 41 asread command signal and is supplied to the comparator 58 as an operationcommand signal. The comparator 58 compares the data sequentially readfrom the RAM 41 with the data from the buffer 45, in accordance with the16-Hz signal. In this case, the comparator 58 compares six-charactername data from the RAM 41 with that from the buffer 45 so as to sort thecontent of the RAM 41 into alphabetical order. In other words, thecomparator 58 performs an edit operation so that names are sorted intothose having "A" as the first character and those having "Z" as thefirst character. In the case of names having the same first character,they can be sorted into alphabetical order from the second character.For this reason, when data from the buffer 45 has a lower alphabeticalorder than that from the RAM 41, the comparator 58 transfers the data tothe RAM 41 again. When the comparator 58 detects the data from thebuffer 45 having the upper alphabetical order than that from the RAM 41,it transfers the data to the RAM 41. When the content of the addresscounter 42 is at the final address, an end signal E is supplied to an Rinput terminal of the SR-FF 63. The 16-Hz signal from the AND gate 64 issupplied to the display controller 14 as the display control signal 15ais described above. In this case, the display controller 14 makes thematrix display portion 1A of the display unit 1 perform a predetermineddisplay representing the edit operation.

Operation of the embodiment will be described hereinafter. FIGS. 7A to7C are views showing changes in display states in accordance with theoperation of the switch S1. When a signal 29a is generated from the modeselector 29, since the gate circuit 17 is enabled, the content of thecounter 13 is supplied to the display unit 1 to be displayed. In thismanner, the timepiece mode in which the content of the counter 13 isdisplayed on the display unit 1, a current time, for example, Sep. 28th,1983, Wednesday, 10 (hours): 58 (minutes) 50 (seconds) PM as shown inFIG. 7A is displayed on the display unit 1. In the normal timepiecemode, when the switch S1 is depressed once, the mode selector 29generates a signal 29a, thereby enabling the gate circuit 20. Thus, thedisplay mode is switched to the telephone number display mode in whichthe data read out from the data memory circuit 15 is displayed. In thetelephone number display mode, the switching controller 16 generates thesignal e1 which is supplied to the data memory circuit 15. Then, in thecircuit 15 the rising detector 47 generates the one-shot pulse insynchronism with raising the signal e1, thereby enabling the AND gate44. As a result, the data from the RAM 41 designated by the addresscounter 42 is written in the buffer 45, and thereafter is supplied tothe display unit 1 through the gate circuit 21 so as to be displayed,e.g., as shown in FIG. 7B. The name data of 6 characters isalphabetically displayed on the 6-digit matrix display portion 1A, andthe telephone number data is digitally displayed on the sub and maindigital display portions 1B and 1C of 12 digits. In this case, when thedesired name data cannot be obtained, the switch S5 or S6 is depressed.Since the RAM 41 stores the name data in alphabetical order, it isdetermined that if the desired name data is stored after or before thecurrent displayed name data with reference thereto. If the desired namedata is stored after the current name data, the switch S5 is operated,and if before the current data, the switch S6 is operated. In thetelephone number display mode, when the switch S5 or S6 is operated, theswitch controller 16 generates the signal e5 or e6 in response to theoperation of the corresponding switch so as to increase or decrease thecontent of the address counter by one and to enables the and gate 44.Thus, the subsequent or preceding telephone number data is read out fromthe RAM 41 and is displayed. Every time the switch S5 or S6 is operated,the address of the RAM 41 is increased or decreased by one and thesubsequent or preceding telephone number data is sequentially displayed.Therefore, the switch S5 or S6 is operated until the desired name datais displayed. When the next address of the RAM 41 is designated byoperating the switch S5 and when the address at which no data is stored(empty address) is designated first, the data empty detector 55 detectsthat all the digits have no data and generates the signals 15a and G inresponse to this. As a result, hyphens are displayed on all the digits(12 digits) of the sub and main digital display portions 1B and 1C, asshown in FIG. 8A. Simultaneously, the AND gate 59 is enabled by thesignal G. In this state, when the switch S5 is depressed once more, theaddress counter 42 is cleared to "00000". As a result, the start addressof the RAM 41 at which the character and numerical data of, e.g., "AOKI0552-41-628" is stored is designated. Therefore, since the first page atwhich the data is stored is displayed after the hyphens are displayed onall the display digits (i.e., empty page display), the empty pagedisplay can serve to clearly divide the first and last pages.

In the telephone number display mode, when the switch S1 is depressedonce, the mode selector 29 generates the signal 29c so as to enable thegate circuit 20. Thus, the alarm time data and the message data for thealarm time are read out from the alarm circuit 18 and are displayed.FIG. 7C shows the display state in the alarm time display mode. When theswitch S1 is depressed once more, the display mode returns to thetimepiece mode, as shown in FIG. 7A.

The operation for setting or correcting the telephone number data willbe described. In the telephone number display mode, the switch S2 isoperated so as to set the T-FF 9 of the switching controller 16. Sincethe controller 16 generates the signal e2, the AND gates 48 to 50 arerespectively opened in the data memory circuit 15. In this state, whenthe switch S3 is depressed first, the content of the digit selector S3is updated by the signal e3. After selecting the digit to be set, whenthe switch S4 is operated, the signal generated in response to theoperation of the switch S4 is supplied to the character data generator51 and the numerical data generator 52. Assuming that the first to sixthdigits of the buffer 45 are selected one of characters "A" to "Z" iswritten in alphabetical order in one of the selected digits every timethe switch S4 is operated. Assuming that the seventh to 18th digits areselected, one of the numerals "0" to "9" is written in one of theselected digits every time the switch S4 is operated. In this case,since the data written in the buffer 45 is sequentially displayed, thedisplay content can be visually observed. So, the switch S4 can bedepressed until the desired character or numeral data is displayed. Thedata written in the buffer 45 is supplied to the data empty detector 55which checks the presence/absence of the data. Thus, the signal 15acorresponding to the data empty digit is generated and is supplied tothe display controller 14. Now assuming that the telephone number datais being written and the last two digits are not set, hyphens aredisplayed on the digits corresponding to the data empty digits, as shownin FIG. 8B. In this manner, a user can confirm that the last two digitsmust be set. Before setting the telephone number data in the buffer 45,since hyphens are displayed on all the digits of the digital displayportions in the same manner as in the empty page display of FIG. 8A, thenumber and positions of the digits to be set are clear. This results inconvenience when data such as telephone number data is set to be dividedat predetermined positions when the data is set to be divided atpredetermined digits so as to allow easy reading at a later time.

In this manner, when setting the operation of the data in the buffer 45is completed, the switch S2 is operated again. The output of the T-FF 9is inverted and the signal e2 goes to the low level (logic level "0").AS a result, since the one-shot pulse is generated from the fallingdetector 62, the content of the address counter 42 is cleared to"00000", thus designating the start address of the RAM 41.Simultaneously, the SR-FF 63 is set so as to enable the AND gate 64.Thus, the AND gate 64 generates a 16-Hz signal which is supplied to theRAM 41, the address counter 42 and the comparator 58. The comparator 58compares the data sequentially supplied from the start address of theRAM 41 with the data from the buffer 45, and executes the edit operationso as to sort the content of the RAM 41 into alphabetical order inaccordance with the comparison result. The content of the RAM 42 issorted into name data having "A" as the first character to that having"Z" as the first character, and in the case of the name data having thesame first character, they can be sorted into alphabetical order fromthe second character. In other words, every time new data is inputted,the RAM 41 is edited. During the edit operation, since the 16-Hz signalfrom the AND gate 64 is supplied to the display controller 14, "SET-A"is, for example, displayed on the matrix display portion 1A of thedisplay unit 1, as shown in FIG. 1. In this case, one letter isdisplayed next to a hyphen in the order of "A" to "Z" in accordance withthe 16-Hz signal. During the edit operation, when the content of theaddress counter 42 reaches the final address of the RAM 41 and the endsignal E is thus generated, the SR-FF 63 is reset. In this manner, theedit operation is stopped in response to the signal E.

Before executing the edit operation described above, the error datadetector 56 checks if the format of data written in the buffer 45coincides with a preset given format. When the detector 56 directscoincidence between them, the output therefrom becomes "0" and theoutput from the inverter 61 thus becomes "1", thereby enabling the ANDgate 57. The data written in the buffer 45 is supplied to the comparator58 and is written in the RAM 41 in accordance with the above-mentionededit operation. On the other hand, when the detector 56 detects errordata, the output therefrom becomes "1", thus disabling the AND gate 57.Even when the above edit operation is performed, the error data cannotbe written in the RAM 41 and is ignored.

In the above embodiment, the telephone number data is stored in the datamemory. However, the data can be street address data, schedule data andthe like and can be changed as needed. In the above embodiment, thetimepiece mode, the alarm time mode and the telephone number displaymode are switched by operating the switch S1. However, a plurality oftelephone number display modes and corresponding data memory circuits 15can be provided so as to perform the operation in the above embodiment.For example, telephone number display modes A and B can be switched by aswitch so that a data memory corresponding to the telephone numberdisplay mode A stores business telephone number data and another datamemory corresponding to the telephone number display mode B storesprivate telephone number data. In both the display modes, theabove-mentioned operation can be performed. In this case, the datamemory for the display modes A and B can be configurated by a singleRAM.

The data input means is not limited to a push-button switch. Forexample, the data input means can be a touch switch formed on a glasssurface of a wristwatch which is touched so as to manually write adesired character with a finger.

In the above embodiment according to the present invention, variouscircuits comprise hardware. However, various functions can be controlledby a microprogram stored in a read-only memory (ROM), and functionsother than the above-mentioned ones can be provided. Another embodimentof the present invention will be described hereinafter. Note that thesame reference numerals as in the above embodiment denotes the sameparts in this embodiment, and a detailed description thereof is omitted.

FIG. 9 shows the overall circuit configuration. A reference frequencysignal genrated by an oscillator 107 is frequency-divided by a frequencydivider 108 and is supplied to a timing signal generator 109. Variousbasic timing signals generated by the generator 109 are supplied to aROM 110, a RAM 111, a command decoder 112 and an address counter orcontroller 113 so as to drive them.

The ROM 110 stores microprogams for controlling the overall operation ofthis electronic wristwatch. Each microprogram is read from an area ofthe ROM 110 whose address is designated by the address controller 113 soas to be executed. Operation code data of the read program is suppliedfrom a terminal OP of the ROM 110 to the command decoder 112, andnumerical value and address data thereof are supplied from a terminal DOof the ROM 110 to an address input terminal Addr of the RAM 111, theaddress controller 113, and an input terminal D12 of a calculation unit114 through a data bus. The next address data is supplied to the addresscontroller 113

The decoder 113 decodes the operation code data and supplies aread/write control signal to the RAM 111. The decoder 112 also suppliesa calculation command to the calculation unit 114. The data read from aterminal DO of the RAM 111 is supplied to terminals D11 and D12 of thecalculation unit 114. The calculation unit 114 calculates in accordancewith the current calculation command. The calculation data is suppliedto a terminal D1 of the RAM 111 and is written therein. A "0 " signaland a carry signal generated by the calculation unit 1124 are suppliedto the address controller 113 so as to change an access address of theROM 110 in accordance with the calculation result of the unit 114. A32-Hz timing clock generated from the frequency divider 108 is alsosupplied to the address controller 113. In response to this, thecontroller 113 supplies the address data for reading a program of atiming flow executed every 1/32 seconds, and the calculation unit 114calculates to obtain new timing data in response thereto. The unit 114supplies the calculation result to the RAM 111.

The data read from the RAM 111 is supplied to a decoder 115 so as to beconverted into display data and is displayed on the same display unit 1as that shown in FIG. 2. An input unit 116 comprises switches S3, S5,S6, S4, S2 and S1 and input data from these switches are written in theRAM 111 through a data bus.

FIG. 10 shows the memory map of the RAM 111. As shown in FIG. 10, theRAM 111 comprises at least T, D, M, L, n, N, P, S and F_(SE) registersand data storing page registers Q1 to Q50. Time data or date data isstored in the T and D registers in the timepiece mode. The M register isa flag register in which "0" is set in the timepiece mode and "1" is setin the memory mode. The L register is also a flag register in which "0"is set in the read out mode and "1" is set in the write mode. The nregister stores the number of pages (the number of registers) in whichdata is stored. The N register stores the maximum number of pages whichcan be stored. The number of display pages is set in the P register. Theuppermost page of the set pages is set in the S register. The F_(SE)register is a flag register used for editing. Data such as telephonenumber data is set in the registers Q1 to Q50, and the number ofregisters corresponds to the number of pages. In this case, in eachpage, letters (characters) up to 6 digits and numerals up to 12 digitscan be set.

Operation of this embodiment will be described with reference to FIGS.11 to 15. The overall operation will first be described with referenceto a general flow of FIG. 11 and representations of FIG. 14. When thecalculation unit 114 supplies the 32-Hz signal to the address controller113, the controller 113 reads a count program from the ROM 110 to causethe calculation unit 114 to perform the count calculation (step G1). Inthis case, the preceding time and data data are read out from the T andD registers of the RAM 111 and predetermined values are respectivelyadded thereto. Thus, the current time and data data are set in the T andD registers.

After completing the count processing, it is checked if the switch S1for switching the timepiece mode or the memory mode has been operated(step G2). If NO in step G2, the flow jumps to step G6 and it is checkedif the data of the M register is "0". If YES in step G6, this means thedevice is in the timepiece mode and the display processing of step G7 isperformed. Then, as shown in A in FIG. 14, the ata of the T and Dregisters are supplied to the display unit 1 so as to display the timeand date. Thereafter, it is checked if an interrupt processing signalhas been given (step G8). If YES in step G8, interrupt processing isexecuted, and if NO in step G8, the device is set in th stand-by modeuntil the next general flow execution.

On the other and, if YES in step G2, the flow advances to step G3 and itis checked if the data of the M register is "1". If YES in step G3, thismeans the device set the timepiece mode. If NO in step G3, this meansthe device is in the timepiece mode, and the flow advances to step G5.In step G5, flag "1" is set in the M register so as set the memory mode.Then, the flow advances to the display processing of steps G6 and G7.Thus, as shown in FIG. 14, when it is the display shown in referencesymbol A in the timepiece mode and the switch S1 is then operated, it ischanged to the display shown in reference symbol B in the memory mode soas to display the telephone number. If the display is indicated inreference symbol B in the memory mode and the switch S1 is thenoperated, the display mode is switched to the timepiece mode.

If M is not "0" in step G6, i.e., if the memory mode is set, the flowadvances to step G9, and the write or read mode is switched. In step G9,it is checked if the switch S2 has been operated. In NO in step G9, theflow jumps to step G14, and it is checked if the L register is "0". IfYES in step G14, this means the device is in the read out mode, and theflow advances to step G15. In step G15, it is checked if the F_(SE) flagregister for editing is "0". If YES in step G15, the read processing(step G16) is executed, and therafter the flow advances to step G8. Onthe other hand, if NO in step G15, the write processing (stp G17) isexecuted and thereafter the flow advances to step G8.

In NO in step G15, this means the device is in the write mode, the flowadvances to step G17 so as to execute write processing.

Operation of the write processing in step G17 will be described withreference to FIGS. 12 and 15. When the data is written, the switch S5 orS6 is operated so as to search the data storing registers Q1 to Q50 inthe positive or negative direction, thereby finding an area having nodata. In this case, in step W1, data "51" which is obtained by adding +1to data "50" of the N register storing the maximum page number "50" isset in the S register.

An address of the RAM 111 is designated by the data of the P register inwhich the current display page is set (step W2). The presence of a keyinput is checked in step W3. When the switch S5 of S6 is operated, theflow adances to step W4 and it is checked if the switch S3 is operated.If NO in step W4, the flow advances to step W21 and it is checked if theswitch S5 is operated. If YES ins tep W21, the flow advances to step W22and the P register is incremented by 1 so as to advance the register byone page. In step W23, the data "50" is compared with the data of the Pregister. If N≧P, the flow return to step W2. On the other hand, if N≦P,this means that the current page number exceeds fifty, and therefore theflow advances to step W24. In step W24, flag "1" is set in the Pregister and the display page in returned to the first page. Then, theflow returns to step W2.

On the other hand, when the switch S6 is operated, the flow advancesfrom step W21 to step W25 and it is checked of the switch S6 isoperated. If YES in step W25, the P register is decremented by one pagein step W26. Then, it is checked if the data of the P register is "0",i.e., if the display page is the 0th page (step W27). If NO in step W27,the flow return to step W2 and if YES in step W27, the data "50" of theN register is set in the P register so as to set the fiftieth page.Then, the flow returns to step W2.

When the switch S5 or S6 is operated, the data is read out from theregister corresponding to the page represented by the data of the Pregister which is incremented or decremented by 1 and is displayed onthe display unit 1. When the switch S5 or S6 is repeatedly operated andthe display which represents that no data (telephone number) is writtenin the current page of the P register as shown in A in FIG. 15, theoperation of the switch S5 or S6 is stopped. As a result, as shown in Bin FIG. 15, a cursor is displayed on the first digit of the characterdisplay portion 1A (referring to FIG. 2). In this state, when the switchS4 is operated once, the letter "A" is automatically displayed on thefirst digit. In this case, it is checked if the switch S4 is operated,in steps W3, W4, W21 and W25, and the letter "A" is displayed by theprocessing in step W29. Then, the flow returns to step W3.

In an input operation of telephone numbers, a family name or anabbreviation with six characters is set in the character display portion1A and actual telephone number is set in the numerical display portions1B and 1C. Assuming that the family name of "SUZUKI" and the telephonenumber of "0123-45-7890" are set, the switch S14 is continuouslyoperated until the first letter "S" is displayed in the alphabeticalorder. As shown in C in FIG. 15, when the letter "S" is displayed, theswitch S3 for inputting this letter is operated.

At this time, it is checked if the switch S3 is operated in step W4. Instep W5, the data in the S and P registers are compared. When S≦P, thedata of the current display page of the P register is set in the Sregister (step W5), and the data "S" is transferred to the current pageregister in the RAM 111 (set W7). Then, as shown in D in FIG. 15, thecursor is moved to the second digit (step W8), and the data "S" isstored in the current page register. The flow then returns to step W3.

Other letters "SUZUKI" can be inputted by the operation of the switchesS4 and S3, in the same manner as described above. As shown in referencesymbol E in FIG. 15, when the last letter "I" is inputted and is storedby the switch S3, the cursor as shown in reference symbol F in FIG. 15is moved to the first digit of the upper column of the numeral displayportion 1B. Thereafter, every time the switch S4 is operated, numeralsare displayed as 0 1, . . . , 9 in the order named. Thus, when thedesired numeral is displayed, the switch S3 is operated so as to storeit in the current page register. G, H and I in FIG. 15 illustrate theinput operation. When the data for one page has been inputted, the nextpage is designated by the switch S5 or S6 and the data is stored in thesame manner as described above.

In this manner, when the desired number of data have been stored in thedata storing registers Q1 to Q50 in the RAM 11, no key operation isneeded. Then, the flow advances from step W3 to step W10. In step W10,it is checked if the flag F_(SE) is "1". Flag F_(Se) is set at "1"because the write processing is being executed. For this reason, theflow advances to step W11, and the data of the S register is comparedwith the data "50" of the N register. In this case, if the inputoperation is being carried out, the relation S≦N is always established.Therefore, the edit operation of step W12 is executed. However, if theinput operation is not performed S>N is established from the processingof step W1 and the write processing ends.

In the edit operation of step W12, 6-character data in the respectivedata storing registers Q1 to Q50 are sorted into alphabetical order.When this operation ends, flag F_(SE) is set at "0" in step W13, and theoperation from step W14 to step W20 is repeatedly performed so that theactual data number in the RAM 111, i.e., the number n of the registersused among the registers Q1 to Q50 is calculated.

In steps W14 and W15, data "0" is set in the n register and data "1" isset in the P register. A Pth page, i.e, the first page of the RAM 111 isdesignated (step W16) and it is checked if the data is stored therein(step W17). If YES in step W17,the n register is incremented by 1. If NOin step W17, the flow jumps to step W19. It is checked in step W19 ifthe data of the P register is equal to the data "50" of the N register,i.e., the retrival operation of data is performed to the fiftieth page.The flow advances to step W20 until the fiftieth page is reached and theP register is incremented by 1 so as to designate the next page. In thismanner, steps W16 to W20 are repeated 50 times so as to obtain thenumber n of the registers used. When N=P, the flow ends.

Operation of the read processing o step G16 will be described withreference to FIGS. 13 and 16. In this case, when the data in theregisters Q1 to Q50 are sequentially read so as to be displayed, theswitch S5 or S6 is operated. On the other hand, when the number ofregisters used must be displayed, the switch S4 is continuouslydepressed.

For example assume that the switch S5 is operated. In step R1, it ischecked if the switch S5 is operated. Since YES in step R1, the lowadvances to step R2. In step R2, it is checked if the data of the nregister (the number of the registers having data) is "0". If .[.YES.]..Iadd.NO .Iaddend.in step R2, since no data is stored in any storingregisters Q1 to Q50, the flow advances to step R7 and the data displayprocessing of the current page is performed. In this case, since no datais stored in this page, hyhens representing a data empty state aredisplayed as shown in D in FIG. 16.

If .[.NO.]. .Iadd.YES .Iaddend.in step R2, the flow advances to step R3,and the data of the P register is compared with the data of n register.If P<n, the flow advances to step R5, and the next page is designated soas to display the data thereof (stp R7). If P=n, the flow advances tostep R4, and it is checked if the data of the n register is equal to thedata "50" of the P register, i.e., if all the registers Q1 to Q50 havethe ata. If YES in step R4, the flow advances to step R6 and the currentdisplay page is returned to the first page so as to display the datathereof (step R7). If NO in step R4, the flow advances to step R5 andthe next page is designated, thus displaying the data thereof (step R7).Furthermore, if P>n in step R3, the flow advances to step R6 and thedisplay page is returned to the first page, thus displaying the datathereof (step R7).

In this manner, every time the switch S5 is operated, steps R1 to R7 areselectively executed in accordance with the relationship between thecurrent display page and the used register number of the n register soas to sequentially designate the pages, thus displaying the datathereof. In FIG. 16, the flow A, B, C,. D, A. . . . , represents thisopration. For example, assume that among the registers Q1 to Q50, thedata is stored in the registers Q1 to Q20 and the page number of the Pregister is the third page when the read processing is started. First,the data of the third page is displayed, and every time the switch S5 isoperated once, the data in the fourth, fifth, sixth, . . . , 19th, and20th pages are sequentially displayed. When the page number reaches the21st page in which no data is written, hyphens shown in D in FIG. 16 aredisplayed. Thus, the display page is returned to the first page and thedata in the first, second, third, fourth, . . . 20 pages are displayed.In this manner, hyphens indicating the data empty state of the 21st pageare displayed, and the display page is returned to the first page again.

Since the switch S6 is used for addressing the RAM 111 in the negativedirection opposite to the case of the switch S5, the processing of stepsR5 to R14 is obvious to those skilled in the art and a detaileddescription thereof is omitted.

In order to obtain the number of registers used, when the switch S4 isdepressed, for example, "27/50" is displayed during the depressioninterval. Note that "27" represents the number of registers used and"50" represents the maximum page number.

When the switch S4 is depressed, the flow advances to step R15 throughsteps R1 and R3 and the depression thereof is checked. Thereafter, asshown in E in FIG. 16, the processing for displaying the number ofregisters used (step R16) is executed.

It should be noted that in the above embodiment, the used page number isdisplayed. However, the remaining page number can be displayed. In theabove embodiment, when the latest data which is written in one of thedata storing registers Q1 to Q50 is displayed, hyphens which representthe data empty state are displayed. Instead of this, for example,assuming that the data is stored in each of the registers Q1 to Q50 andthe register 5 is first displayed when the memory mode is selected, thehyphen display such as 5, 6, 7, 8, 9, 10, 1, 2, 3, 4, hyphens, 5, and 6can be performed. Furthermore, in the data edit operation, the order ofdata is not limited to the alphabetical order. The present invention canbe applied not only to an electronic wristwatch but also to any smallelectronic equipment with a memory.

What is claimed is:
 1. A portable electronic memorandum device,comprising:character data item input means for inputting character dataitems including at least character data; character data item-storingmeans for storing the character data items inputted by said characterdata item input means; operation switching means for sequentiallydesignating the character data items in the character data item-storingmeans, and for sequentially reading out the character data items storedin the character data item-storing means in response to a switchingoperation; optical display means for sequentially displaying thecharacter data items sequentially read out by said operating switchingmeans; .[.empty.]. display control means (.Iadd.a) .Iaddend.for enablinga last character data item stored in said character data item-storingmeans to be displayed on said optical display means when operating saidoperation switching means .[.and.]. (.Iadd.b) .Iaddend.for thereafter,when operating said operation switching means, causing .[.a.]. display.Iadd.of indicia on said optical display means .Iaddend.representing.[.a data empty state to be indicated on said optical display means whenoperating said operation switching means; and first character datadisplay control means.]. .Iadd.that the last character data item hasbeen read out, and (c) .Iaddend.for permitting a first character dataitem stored in said data item-storing means to be displayed on saidoptical .[.dispaly.]. .Iadd.display .Iaddend.means when operating saidoperation switching means after .[.the data empty state is indicated.]..Iadd.said indicia have been displayed .Iaddend.by operation of said.[.empty.]. display control means.
 2. A device according to claim 1,wherein said optical display means comprises means for displaying thenumber of character data items stored in said character dataitem-storing means.
 3. A device according to claim 1, wherein saidoptical display means comprises means for displaying the number ofcharacter data items which can be stored in said character dataitem-storing means.
 4. A device according to claim 1, wherein saidcharacter data item storing means includes means for storing thecharacter data items in alphabetical order.
 5. A device according toclaim 1, comprising input control means for enabling said character dataitem input means to input a new character data item .[.when the dataempty state is indicated.]. .Iadd.upon display of said indicia.Iaddend.by operation of said .[.empty.]. display control means.
 6. Adevice according to claim 5, comprising means for causing .[.the dataempty state display to be indicated.]. .Iadd.said indicia to bedisplayed .Iaddend.again, after the new character data item has beeninput by use of said imput control means.
 7. A device according to claim1, wherein said .[.empty.]. display control means includes means forenabling said optical display means to display hyphens .[.to indicatethe data empty state.]. .Iadd.as said indicia to represent that the lastcharacter data item has been recalled.Iaddend..
 8. A device according toclaim 1, comprising edit means for re-storing the plurality of thecharacter data items which have been stored in said character dataitem-storing means, and a charcter data item newly inputted, in an orderaccording to a predetermined format.
 9. A device according to claim 8,comprising means for indicating that said edit means is operating.
 10. Adevice according to claim 8, wherein said edit means comprises means forsorting and re-storing in alphabetical order, the plurality of characterdata items stored in said character data item-storing means and thecharacter data item newly inputted.
 11. A portable electronic memorandumdevice, comprising: .[.characteristic.]..Iadd.character .Iaddend.dataitem input means for inputting character data items including at leastcharacter data; character data item-storing means, having a plurality ofaddress areas, for storing the character data items inputted by saidcharacter data item input means, in an order according to aspredetermined format .[.and including an address area which is empty ofdata.]., operation switching means for sequentially designating therespective address areas in the character data item-storing means, andfor sequentially reading out the character data items stored in thedesignated address areas in response to a switching operation; opticaldisplay means for sequentially displaying the character data itemssequentially read out by said operation switching means; detecting meansfor detecting .[.if the empty address area is designated after addressareas corresponding to.]. .Iadd.that .Iaddend.all character data itemsstored in the character data item-storing means .[.are.]. .Iadd.havebeen .Iaddend.designated by operation of said operation switching means;.[.empty173 display control means for causing .[.a.]. display .Iadd.onsaid optical means of indicia .Iaddend.representing .[.a data emptystate to be indicated on said optical display means.]. .Iadd.that allsaid stored character data items have been designated.Iaddend., on thebasis of an output from said detecting means .[., first character datadisplay control means, and .Iadd..Iaddend.for permitting a firstcharacter data item stored in said .Iadd.character .Iaddend.dataitem-storing means to be displayed on said optical display means whenoperating said operation switching means after .[.the empty state isindicated.]. .Iadd.said indicia have been displayed .Iaddend.byoperation of said .[.empty.]. display control means.
 12. A deviceaccording to claim 11, wherein said character data item-storing meansincludes means for storing the character data items in the sequentialaddress areas in alphabetical order.
 13. A device according to claim 11,comprising input control means for enabling said character data iteminput means to input a new character data item .[.when the data emptystate is indicated.]. .Iadd.upon display of said indicia .Iaddend.byoperation of said .[.empty.]. display control means.
 14. A deviceaccording to claim 13, comprising means for causing .[.the data emptystate display to be indicated.]. .Iadd.said indicia to be displayed.Iaddend.again, after the new character data item has been input by useof said input control means.
 15. A device according to claim 11, whereinsaid .[.empty.]. display control means includes means for enabling saidoptical display means to display hyphens .[.to indicate the data emptystate. .Iadd.as said indicia to represent that all stored character dataitems have been designated.Iaddend..
 16. A device according to claim 11,comprising edit means for re-storing the plurality of the character dataitems which have been stored in said character data item-storing means,and a character data item newly inputted, in an order according to saidpredetermined format.
 17. A device according to claim 16, comprisingmeans for indicating that said edit means is operating.
 18. A deviceaccording to claim 16, wherein said edit means comprises means forsorting and re-storing, in alphabetical order, the plurality of thecharacter data items stored in said character data item-storing means ina character data item newly-inputted.
 19. A portable electronicmemorandum device, comprising:character data item input means forinputting character data items including at least character data;character data item-storing means, having a plurality of address areas,for storing the character data items inputted by said character dataitem input means, in an order according to a predetermined format .[.andincluding an address area which is empty of data; operation switchingmeans for sequentially designating the respective address areas in thecharacter data item-storing means, and for sequentially reading out thecharacter data items stored in the designated address areas in responseto a switching operation; optical display means for sequentiallydisplaying the character data items sequentially read out by saidoperation switching means; .[.empty.]. display control means (.Iadd.a).Iaddend.for causing a last character data item stored in said characterdata item-storing means to be displayed on said optical display meanswhen operating said operation switching means, .[.and.]. .Iadd.(b).Iaddend.for thererafter .Iadd.when operating said operation switchingmeans .Iaddend.detecting .[.the empty address area.]. .Iadd.that thelast character data has been read out .Iaddend.and causing .[.a.].display .Iadd.of indicia on said optical display means.Iaddend.representing .[.a data empty state to be indicated on saidoptical display means when operating said operation switching meansagain; and first character data display control means.]. .Iadd.that thelast character data item has been retrieved, and (c) .Iaddend.forpermitting a first character data .[.items.]. .Iadd.item .Iaddend.storedin said data item-storing means to be displayed on said optical displaymeans when operating said operation switching means after .[. the dataempty state is indicated.]. .Iadd.said indicia have been displayed.Iaddend.by operation of said .[.empty.]. display control means. 20..Iadd.A device according to claim 1, wherein said display control meanscauses display of said indicia upon a next operating of said operationswitching means following display of said last character data item byoperating said operation switching means. .Iaddend.
 21. .Iadd.A deviceaccording to claim 1, wherein said display control means permits thefirst character data item to be displayed upon a next operating of saidoperation switching means following display of said indicia by operatingsaid operation switching means. .Iaddend.
 22. .Iadd.A device accordingto claim 11, wherein said display control means permits the firstcharacter data item to be displayed upon a next operating of saidoperation switching means following display of said indicia by operatingsaid operation switching means. .Iaddend.
 23. .Iadd.A device accordingto claim 19, wherein said display control means causes display of saidindicia upon a next operating of said operation switching meansfollowing display of said last character data item by operating saidoperation switching means. .Iaddend.
 24. .Iadd.A device according toclaim 19, wherein said display control means permits the first characterdata item to be displayed upon a next operating of said operationswitching means following display of said indicia by operating saidoperation switching means. .Iaddend.